Dynamic Random Access Memories (DRAMs), because of their single transistor/single capacitor per cell structure, are on the forefront of memory density and capacity in spite of inherent disadvantages which are well known in the art. For example the single transistor/single capacitor structure is characterized by a relatively weak storage signal, in addition to the obvious requirement for periodic refreshing of the memory cell capacitor.
Special circuits have been developed in the past to compensate for this relatively weak storage signal. The most common circuitry for sensing the signals stored in the capacitor of the cell has been a differential cross-coupled amplifier situated between two halves of a bit line. In this circuit the signal on the cell capacitor is sensed by first coupling the cell capacitor to one of the half bit lines to equilibrate the cell capacitance voltage and the bit line voltage. Next, the sense amplifier detects and amplifies this voltage imbalance in the two bit line halves. The capacitance and charge of the memory cell is very slight in comparison to the bit line itself, since the bit lines have many times more parasitic capacitance than the capacitance of the memory cell. Therefore, the signal is very small. After the signal is sensed, the memory capacitor is either recharged to a high voltage or completely discharged depending on the polarity of the signal to be stored.
More specifically, the sense amplifier generally uses two matched cross-coupled field effect transistors (FETs), with the drain of each FET connected to one half of the bit line and also to the gate of the other FET. The sources of the two FETs are common and attached to a latch signal line. Sensing occurs by initially placing a voltage on the bit line, which is greater than the threshold voltage of the two FETs. Next, the selected memory cell is connected to one of the bit line halves to create an imbalance in the voltage of the two bit lines halves. Because of the voltage difference between the two half bits lines, as the latch signal line is pulled downward one of the cross coupled FET's (the one with the higher gate voltage) begins to become conductive. This starts to discharge the bit line at the lower voltage and prevents the other FET from conducting. As the latch signal line is pulled to the ground potential, the lower potential bit line follows to ground while the higher potential bit line remains where it began. In this manner a full logic level difference can eventually be developed between the bit line halves.
Of particular importance with regard to the invention disclosed below is the necessity to precharge the bit line halves to a voltage greater than the threshold voltage of the FETs. In practice, the precharge is much higher than the threshold voltages for several reasons not directly related to the operation of the two cross-coupled FETs. However, this precharge to a relatively high voltage takes precious time and also produces several problems which adversely affect the cycle time and signal margins of the memory.
For example, the bit lines are precharged by FET transistors which exhibit a lower and more uniform onresistance when the gate-to-source voltage is relatively large. However, as the bit lines approach the supply voltage of the memory, the gate-to source voltage of the precharged FETs decreases, causing the bit line voltage to rise at a decreasing rate, thereby necessitating a relatively long precharge operation to insure uniform precharge voltages. Moreover, the final precharge voltage differential between the two bit line halves is determined by the characteristics of the precharge transistors when they have a relatively small gate-to-source voltage, as compared to two FETs which operate at a greater gate-to-source voltage.
Although the above described sense amplifier is sensitive to small changes in the bit line voltage, its output is relatively slow to develop and is generally used with another amplifier to speed the process of developing full logic levels. However, the scond sense amplifier cannot be coupled to the first sense amplifier during the sensing operation of the first amplifier, and thus there is the added time delay required by the second sense amplifier before a logic level is present on the digit line.
Therefore it can be appreciated that a dynamic random access memory sense amplifier which provides a rapid and accurate precharge and which provides for a faster overall memory access time is highly desirable.